1. Field of the Invention
The present invention relates to a defect analysis method for analyzing the cause of defectiveness in electric characteristics or the like of a semiconductor device which is capable of inspecting the presence or absence of defects in a product during the manufacturing process.
2. Background of the Invention
Conventionally, a semiconductor device such as a DRAM or a micro computer has been manufactured through a plurality of manufacturing processes. After those processes have been completed, a total defective/non-defective test on the electric characteristics has been carried out to obtain an yield of the device. On the other hand, after a specified process out of the plurality of manufacturing processes, inspection by an inspection apparatus has been carried out to detect a defect.
Now, we will describe several types of defects to be detected by the inspection apparatus. The defects include a pattern defect, a particle, adhesion of contaminants (stains), damage, or the like. The pattern defect includes short (two wires or layers to be generally isolated are short-circuited), breaking of wire (wires or layers to be generally connected are disconnected), abnormality in shape (the shape of a pattern is abnormal), or the like. A probable cause of the short or the breaking of wire is, for example, patterning with a particle used as a mask. The particle is considered to include an adhered particle, etching residual, or the like. An example of the adhesion of contaminants is adhesion of contaminants in a wet tub. The damage can occur, for example, when a handling error makes a scratch on a wafer.
In defect analysis, the influence of a specified process on the yield of the semiconductor device can be inspected by comparing the yield of the semiconductor device obtained after the manufacturing processes and the number of defects detected after the specified process.
The number of defects detected at the specified process is, however, highly unstable because it can be increased when an unusual number of defects or an aggregate defect is included in a single chip, or because it can be unreliable when the defects detected after the specified process includes a large number of defects due to previous processes. Thus, only a low-reliable correlation is available from a simple comparison between the number of defects detected at the specified process and the yield of the device. This creates a great difficulty in improving accuracy in analyzing the influence of the specified process on the yield of the device.
A first aspect of the present invention is directed to a defect analysis method of a device which includes an integrated circuit formed through a plurality of processes on each of a plurality of chips on a wafer. The defect analysis method comprises the steps of: (a) after each of at least one process out of the plurality of processes, detecting a new defect caused by at least one process and occurring in a new area of the wafer other than an area of a defect occurring at a previous process and its vicinity; (b) after the plurality of processes are completed, making a defective/non-defective judgment on the integrated circuit on each of the plurality of chips is; (c) judging the presence or absence of the new defect satisfying a predetermined identifying condition, for each of the plurality of chips for each of at least one process; (d) classifying the plurality of chips into four groups on the basis of a combination of the judgment of the step (b) and the judgment of the step (c), for each of at least one process; and (e) calculating the number of new defective chips considered to be caused only by the new defect of at least one process, on the basis of the fourfold classification of the step (d).
According to a second aspect of the present invention, the defect analysis method further comprises the step of: (f) calculating a critical rate of the new defect of at least one process, at which a chip is considered to become defective, on the basis of the fourfold classification of the step (d).
According to a third aspect of the present invention, the defect analysis method further comprises the step of: (g) calculating the number of process defective chips considered to be caused by at least one process, on the basis of the fourfold classification of the step (d) and the critical rate.
According to a fourth aspect of the present invention, in the defect analysis method, the step (c) is performed a plurality of times by using each of a plurality of detection sizes as a referred detection size, wherein the predetermined identifying condition includes a condition that a defect be of not less than the referred detection size; and the steps (d) to (g) are performed the plurality of times corresponding to the step (c) performed the plurality of times, so that data for analysis consisting of the number of new defective chips, the critical rate, and the number of process defective chips are obtained for each of the plurality of detection sizes for each of at least one process.
According to a fifth aspect of the present invention, the defect analysis method further comprises the step of: (h) after the steps (c) to (g) are performed the plurality of times, recognizing at least one of the following as an analysis result of at least one process on the basis of the data for analysis: an absolute critical detection size which is the minimum detection size for 100% of the critical rate out of the plurality of detection sizes; the maximum number of process defective chips out of the numbers of process defective chips obtained for each of the plurality of detection sizes; an optimum-sensitivity detection size corresponding to the maximum number of process defective chips, out of the plurality of detection sizes; and the number of optimum-sensitivity new defective chips corresponding to the optimum-sensitivity detection size out of the numbers of new defective chips obtained for each of the plurality of detection sizes.
According to a sixth aspect of the present invention, in the defect analysis method, at least one process includes a predetermined number of processes of not less than two; the data for analysis is obtained for each of the predetermined number of processes, and at the step (h), the maximum number of process defective chips is recognized for each of the predetermined number of processes. The defect analysis method further comprises the step of: (i) ranking the predetermined number of processes according to their necessity for improvement, by comparing the maximum numbers of process defective chips of the predetermined number of processes.
According to a seventh aspect of the present invention, in the defect analysis method, at least one process includes the plurality of processes; the data for analysis is obtained for each of the plurality of processes; and the step (h) includes a step of recognizing the number of optimum-sensitivity new defective chips for each of the plurality of processes. The defect analysis method further comprises the step of: (i) recognizing a degree to which the cause of defectiveness is detected, by comparing a total number of the numbers of optimum-sensitivity new defective chips of the plurality of processes, and the number of chips judged as defective at the step (b).
According to an eighth aspect of the present invention, in the defect analysis method, the device includes a plurality of devices of the same structure each manufactured through the plurality of processes of a plurality of manufacturing lines; the steps (b) to (h) are performed for each of the plurality of devices; and the step (h) includes a step of recognizing the maximum number of process defective chips of at least one process of each of the plurality of manufacturing lines. The defect analysis method further comprises the step of: (i) recognizing superiority or inferiority of the plurality of manufacturing lines by comparing the maximum numbers of process defective chips of at least one process of the plurality of manufacturing lines.
According to a ninth aspect of the present invention, in the defect analysis method, at least one process includes a predetermined number of processes of not less than two which are the same in contents but different inspection apparatus to be used for inspection at the step (a); the data for analysis is obtained for each of the predetermined number of processes; and the critical rate includes the predetermined number of critical rates of the same detection level corresponding to the predetermined number of processes. The defect analysis method further comprises the step of: (h) recognizing a difference in sensitivity between the predetermined number of inspection apparatuses by comparing the predetermined number of critical rates of the same detection level.
According to a tenth aspect of the present invention, in the defect analysis method, the predetermined identifying condition of the step (c) includes a condition that the new defect be in a specific area of the wafer.
According to an eleventh aspect of the present invention, in the defect analysis method, the step (b) includes a step of judging whether each of the plurality of chips is defective or non-defective on the basis of a specific electrical characteristic.
According to a twelfth aspect of the present invention, in the defect analysis method, the predetermined identifying condition of the step (c) includes a condition that a defect be re-detected at the same plane position as the new defect, at a predetermined process after at least one process.
According to a thirteenth aspect of the present invention, in the defect analysis method, the wafer includes a plurality of wafers, and the plurality of chips includes every chip formed on the plurality of wafers.
According to a fourteenth aspect of the present invention, in the defect analysis method, the predetermined identifying condition of the step (c) limits the number of new defects in a single chip.
A fifteenth aspect of the present invention is directed to a storage medium for storing a defect analysis program for having a defect analysis system with a computer execute a defect analysis processing of a device which includes an integrated circuit formed through a plurality of processes on each of a plurality of chips on a wafer. The defect analysis system comprises: at least one inspection apparatus for detecting a position of coordinates of a defect on the wafer and the size of the defect, after each of the plurality of processes, to output defect information; a tester for judging whether each of the integrated circuit on the plurality of chips on the wafer is defective or non-defective after the plurality of processes are completed, to output defective/non-defective judgment information; and a control portion for executing the defect analysis program upon receipt of the defect information and the defective/non-defective judgment information. Further, the storage medium stores the defect analysis program for having the computer execute the steps of: (a) after each of at least one process out of the plurality of processes, detecting a new defect caused by at least one process and occurring in a new area of the wafer other than an area of a defect occurring at a previous step and its vicinity, on the basis of the defect information; (b) after the plurality of processes are completed, making a defective/non-defective judgment on the integrated circuit on each of the plurality of chips on the basis of the defective/non-defective judgment information; (c) judging the presence or absence of the new defect satisfying a predetermined identifying condition, for each of the plurality of chips for each of at least one process; (d) classifying the plurality of chips into four groups on the basis of a combination of the judgment of the step (b) and the judgment of the step (c), for each of at least one process; and (e) calculating the number of new defective chips considered to be caused only by the new defect of at least one process, on the basis of the fourfold classification of the step (d).
A sixteenth aspect of the present invention is directed to a storage medium for storing a defect analysis program for having a defect analysis system with a computer execute a defect analysis processing of a device which includes an integrated circuit formed through a plurality of processes on each of a plurality of chips on a wafer. The defect analysis system comprises: at least one inspection apparatus for detecting a position of coordinates of a defect on the wafer and the size of the defect, after each of the plurality of processes, to output defect information; a tester for making a defective/non-defective judgment on the integrated circuit on each of the plurality of chips on the wafer after the plurality of processes are completed, to output defective/non-defective judgment information; and a control portion for executing the defect analysis program upon receipt of the defect information and the defective/non-defective judgment information, wherein the control portion or at least one inspection apparatus has a function to, after each of at least one process out of the plurality of processes, detect a new defect caused by at least one process and occurring in a new area of the wafer other than an area of a defect occurring at a previous process and its vicinity, on the basis of the defect information. The storage medium stores the defect analysis program for having the computer execute the steps of: (a) receiving a new defect caused by at least one process; (b) after the plurality of processes are completed, making a defective/non-defective judgment on the integrated circuit on each of the plurality of chips, on the basis of the defective/non-defective judgment information; (c) judging the presence or absence of the new defect satisfying a predetermined identifying condition, for each of the plurality of chips for each of at least one process; (d) classifying the plurality of chips into four groups on the basis of a combination of the judgment of the step (b) and the judgment of the step (C), for each of at least one process; and (e) calculating the number of new defective chips considered to be caused only by the new defect of at least one process, on the basis of the fourfold classification of the step (d).
According to a seventeenth aspect of the present invention, in the storage medium, the defect analysis program has the computer further execute the step of: (f) calculating a critical rate of the new defect of at least one process, at which a chip is considered to become defective, on the basis of the fourfold classification of the step (d).
According to an eighteenth aspect of the present invention, in the storage medium, the defect analysis program has the computer further execute the step of: (g) calculating the number of process defective chips considered to be caused by at least one process, on the basis of the fourfold classification of the step (d) and the critical rate.
A nineteenth aspect of the present invention is directed to a process control method for performing an analysis of a device which includes an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes, and then estimating an yield in manufacturing a new integrated circuit on each of a plurality of chips on a new wafer through a plurality of new processes which are identical to the plurality of processes. The process control method comprises the steps of: (a) after each of the plurality of processes, detecting a new defect due to each of the plurality of processes occurring in a new area on the wafer other than an area of a defect occurring at a previous process and its vicinity; (b) after the plurality of processes are completed, making a defective/non-defective judgement on the integrated circuit on each of the plurality of chips; (c) judging the presence or absence of a new defect satisfying a predetermined identifying condition in each of the plurality of chips, for each of the plurality of processes; (d) classifying the plurality of chips into four groups on the basis of a combination of the judgement of the step (b) and the judgement of the step (c), for each of the plurality of processes; and (e) calculating a critical rate of the new defect of each of the plurality of processes, at which a chip is considered to be defective, on the basis of the fourfold classification of the step (d). The analysis includes the steps (a) to (e). The process control method further comprises the step of: (f) calculating an estimated yield of each target process consisting of the plurality of new processes through similar steps to the steps (a) and (c), on the basis of the number of newly detected new defects satisfying the predetermined identifying condition and a critical rate of the target process which is obtained through the analysis of the plurality of processes.
According to a twentieth aspect of the present invention, the process control method of the nineteenth aspect further comprises the step of: (g) after the step (f), calculating a total estimated yield of the plurality of new processes on the basis of the estimated yield of each of the plurality of new processes.
According to a twenty-first aspect of the present invention, in the process control method of the nineteenth aspect, the predetermined identifying condition includes a classification condition that defines a plurality of kinds to classify the new defect. The step (c) includes a step of judging the presence or absence of the new defect of each of the plurality of kinds defined by the classification condition; the step (d) includes a step of classifying the plurality of chips into four groups for each of the plurality of kinds; the number of newly detected new defects includes a plurality of numbers of newly detected new defects corresponding to the plurality of kinds, respectively; the critical rate includes a plurality of critical rates corresponding to the plurality of kinds, respectively; and the step (f) includes a step of calculating an estimated yield of each of the plurality of new processes on the basis of the plurality of numbers of newly detected new defects and the plurality of critical rates.
According to a twenty-second aspect of the present invention, in the process control method of the twenty-first aspect, the plurality of kinds include kinds classified on the basis of a detection size of the new defect.
According to a twenty-third aspect of the present invention, in the process control method of the twenty-first aspect, the plurality of kinds include kinds classified on the basis of the number of the new defects in a single chip.
According to a twenty-fourth aspect of the present invention, in the process control method of the twenty-first aspect, the plurality of kinds include kinds classified on the basis of the presence or absence of the new defect in at least one specific area of the wafer.
According to a twenty-fifth aspect of the present invention, in the process control method of the twenty-first aspect, the plurality of kinds include kinds classified on the basis of the shape of the new defect.
According to a twenty-sixth aspect of the present invention, in the process control method of the twenty-first aspect, the plurality of kinds include kinds classified on the basis of a combination of at least two of the following: a detection size of the new defect; the number of the new defects in a single chip; the presence or absence of the new defect in at least one specific area of the wafer; and the shape of the new defect.
According to a twenty-seventh aspect of the present invention, in the process control method of the nineteenth aspect, the wafer includes a plurality of wafers; and the plurality of chips are formed on the plurality of wafers.
According to a twenty-eighth aspect of the present invention, in the process control method of the nineteenth aspect, the predetermined identifying condition includes a new-defect judgement condition that a new defect out of the new defect which is detected but judged as having no influence on yield should not be regarded as the new defect.
According to a twenty-ninth aspect of the present invention, the process control method of the twentieth aspect further comprises the step of: (h) after the step (g), correcting a total estimated yield of the plurality of new processes to a correction value that is obtained through an analysis of a total estimated yield of a plurality of past processes and an actual yield.
According to a thirtieth aspect of the present invention, in the process control method of the nineteenth aspect, the process (f) includes a step of calculating a middle estimated yield of a predetermined number of processes out of the plurality of new processes, on the basis of an estimated yield of each of the predetermined number of processes.
In the defect analysis method according to the first aspect of the present invention, a plurality of chips are classified into four groups (classification of new defects) on the basis of a combination of the judgment of the step (b) and the judgment of the step (c) about the defectiveness or non-defectiveness of a chip and the presence or absence of a new defect meeting a predetermined identifying condition, respectively. According to the classification, the number of new defective chips considered to be caused only by the new defect of at least one process is calculated.
This makes it possible to quantitatively recognize an increasable number of non-defective chips when at least one process is perfectly improved.
At the step (f) of the defect analysis method of the second aspect, the critical rate of the new defect of at least one process, at which a chip is considered to become defective, is calculated on the basis of the classification of new defects. This makes it possible to quantitatively recognize the sensitivity of an inspection apparatus to detect a defect.
At the step (g) of the defect analysis method of the third aspect, the number of process defective chips considered to be caused by at least one process is calculated on the basis of the classification of new defects and the critical rate. This makes it possible to quantitatively recognize the influence of at least one process on the yield of the device.
In the defect analysis method of the fourth aspect, the steps (c) to (g) are performed for each of a plurality of detection sizes as a referred detection size, to obtain data for analysis including the number of new defective chips, the critical rate, and the number of process defective chips, for each of the plurality of detection sizes for at least one process.
Analysis of the data for analysis makes it possible to compare and examine the number of new defective chips, the critical rate, and the number of process defective chips for each of the plurality of detection sizes.
Further, at the step (h) of the defect analysis method of the fifth aspect, on the basis of the data for analysis, at least one of the following is recognized as an analysis result of at least one process: the absolute critical detection size which is the minimum detection size for 100% of the critical rate out of the plurality of detection sizes; the maximum number of process defective chips out of the numbers of process defective chips for the plurality of detection sizes; an optimum-sensitivity detection size corresponding to the maximum number of process defective chips, out of the plurality of detection sizes; and the number of optimum-sensitivity new defective chips corresponding to the optimum-sensitivity detection size, out of the numbers of new defective chips for the plurality of detection sizes.
This brings about at least one of the following effects: a first effect that the size of the defect which always causes yield deterioration can be recognized from the absolute critical detection size; a second effect that the influence of at least one process on the yield of the device can be accurately recognized from the maximum number of process defective chips; a third effect that an optimum detection size for defect analysis can be recognized from the optimum-sensitivity defection size; and a fourth effect that an increasable number of non-defective chips when at least one process is perfectly improved can be obtained from the number of optimum-sensitivity new defective chips.
At the step (i) of the defect analysis method of the sixth aspect, the predetermined number of processes can be accurately ranked according to their necessity for improvement by comparing the maximum numbers of process defective chips of the predetermined number of processes, irrespective of a difference in the sensitivity to detect a new defect between the predetermined number of processes.
At the step (i) of the defect analysis method of the seventh aspect, a degree to which the cause of defectiveness is detected can be quantitatively recognized for each of the plurality of processes by comparing a total of the numbers of optimum-sensitivity new defective chips of the plurality of processes, and the number of chips judged as defective at the step (b), irrespective of a difference in the sensitivity to detect a new defect between the plurality of processes.
Further, at the step (i) of the defect analysis method of the eighth aspect, superiority or inferiority of at least one process of the plurality of manufacturing lines can be quantitatively recognized by comparing the maximum numbers of process defective chips of at least one process of the plurality of manufacturing lines, irrespective of a difference in the sensitivity to detect a new defect of at least one process between the plurality of manufacturing lines.
At the step (h) of the defect analysis method of the ninth aspect, a difference in sensitivity between the predetermined number of inspection apparatuses can be simply recognized, without any complicate processing, by comparing the predetermined number of critical rates of the same detection level.
In the defect analysis method of the tenth aspect, since the predetermined identifying condition includes a condition that a new defect be in a specific area of a wafer, a correlation between the new defect in the specific area and the yield of the device can be quantitatively recognized.
The step (b) of the defect analysis method of the eleventh aspect includes a step of making a defective/non-defective judgment on each of the plurality of chips on the basis of a specific electrical characteristic. Thus, a correlation between the new defect and the yield of the device can be quantitatively recognized, focusing on the specific electrical characteristic.
In the defect analysis of the twelfth aspect, the predetermined identifying condition includes a condition that a defect be re-detected at a predetermined process after at least one process, at the same plane position as the new defect. Thus, a correlation between the new defect and the yield of the device can be quantitatively recognized in consideration of the degree of the growth of the new defect.
In the defect analysis method of the thirteenth aspect, a wafer includes a plurality of wafers, and a plurality of chips include every chip formed on the plurality of wafers. This increases the number of chips to be analyzed as compared to a case using only a single wafer, thereby increasing statistic reliability of the defect analysis.
In the defect analysis method of the fourteenth aspect, the predetermined identifying condition limits the number of new defects in a single chip. Thus, a correlation between the new defect and the yield of the device can be quantitatively recognized in consideration of the number of new defects.
According to the defect analysis program stored in the storage medium of the fifteenth aspect of the present invention, a plurality of chips are classified (classification of new defects) on the basis of a combination of the judgment of the step (b) and the judgment of the step (c) about defectiveness or non-defectiveness of a chip and the presence or absence of a new defect satisfying a predetermined identifying condition. According to the classification of new defects, the number of new defective chips considered to be caused only by the new defect of at least one process is calculated.
This makes it possible to quantitatively recognize an increasable number of non-defective chips when at least one process is perfectly improved.
According to the defect analysis program stored in the storage medium of the sixteenth aspect, as in the fifteenth aspect, the number of new defective chips considered to be caused only by the new defect of at least one process is calculated on the basis of the classification of new defects.
This makes it possible to quantitatively recognize an increasable number of non-defective chips when at least one process is perfectly improved.
At the step (f) of the defect analysis program stored in the storage medium of the seventeenth aspect, the critical ratio of the new defect of at least one process, at which a chip is considered to become defective, is calculated on the basis of the classification of new defects. This makes it possible to quantitatively recognize the sensitivity of an inspection apparatus to detect a defect.
At the step (g) of the defect analysis program stored in the storage medium of the eighteenth aspect, the number of process defective chips considered to be caused by at least one process is calculated on the basis of the classification of new defects and the critical ratio. This makes it possible to quantitatively recognize the influence of at least one process on the yield of the device.
At the step (f) of the process control method of the nineteenth aspect, an estimated yield of each target process consisting of a plurality of new processes is calculated from the number of newly detected new defects satisfying a predetermined identifying condition and a critical rate of the target process that is obtained through an analysis of a plurality of past processes. This increases accuracy of the estimated yield of each target process.
At the step (g) of the process control method of the twentieth aspect, after the step (f), a total estimated yield of a plurality of new processes is calculated from an estimated yield of each of the plurality of new processes. This increases accuracy of the total estimated yield of the plurality of new processes.
In the process control method of the twenty-first aspect, the predetermined identifying condition includes a classification condition that defines a plurality of kinds to classify new defects. The step (c) includes a step of judging the presence or absence of the new defect of each of the plurality of kinds defined by the classification condition; the step (d) includes a step of classifying the plurality of chips into four groups for each of the plurality of kinds; the number of newly detected new defects includes a plurality of numbers of newly detected new defects corresponding to the plurality of kinds respectively; the critical rate includes a plurality of critical rates corresponding to the plurality of kinds, respectively; and the step (f) includes a step of calculating an estimated yield of each target process out of the plurality of new processes on the basis of the plurality of numbers of newly detected new defects and the plurality of critical rates.
That is, for analysis, the plurality of numbers of newly detected new defects and the plurality of critical rates are first obtained corresponding to the plurality of kinds, for each of a plurality of processes. Then, an estimated yield of each target process out of the plurality of new processes are calculated from the plurality of critical rates obtained for each of a plurality of new processes. This increases accuracy of the estimated yield of each target process.
In the process control method of the twenty-second aspect, a plurality of kinds include kinds classified on the basis of a detection size of the new defect. This increases accuracy in yield estimation even when a particle size distribution of defects over the wafer during analysis is different from that during estimation.
In the process control method of the twenty-third aspect, a plurality of kinds include kinds classified on the basis of the number of new defects in a single chip. This increases accuracy in yield estimation even when an aggregate distribution of defects over the wafer during analysis is different from that during estimation.
In the process control method of the twenty-fourth aspect, a plurality of kinds include kinds classified on the basis of the presence or absence of the new defect in at least one specific area of the wafer. This increases accuracy in yield estimation even when a specific distribution of defects over the wafer during analysis is different from that during estimation.
In the process control method of the twenty-fifth aspect, a plurality of kinds include kinds classified on the basis of the shape of the new defect. This increases accuracy in yield estimation, since the new defect having a specific shape is often closely related to defectiveness of a chip.
In the process control method of the twenty-sixth aspect, a plurality of kinds include kinds classified on the basis of a combination of at least two of the following: a detection size of the new defect; the number of new defects in a single chip; the presence or absence of the new defect in at least one specific area of a wafer; and the shape of the new defect. This considerably increases accuracy in yield estimation even when various conditions of the wafer during analysis are different from those during estimation.
In the process control method of the twenty-seventh aspect, the wafer includes a plurality of wafers; and a plurality of chips include every chip formed on a plurality of wafers. This increases the number of chips to be analyzed as compared to the case using only a single wafer, thereby increasing statistic reliability of the yield estimation.
In the process control method of the twenty-eighth aspect, a predetermined identifying condition includes a new-defect judgement condition that a new defect out of the new defect which is detected but judged as having no influence on yield should not be regarded as the new defect. Thus, an yield can be estimated with high accuracy on the basis of the statistically highly reliable analysis result.
At the step (h) of the process control method of the twenty-ninth aspect, after the step (g), a total estimated yield of a plurality of new processes is corrected to a correction value that is obtained through an analysis of a total estimated yield of a plurality of past processes and an actual yield. This increases accuracy in yield estimation.
The step (f) of the process control method of the thirtieth aspect includes a step of calculating a middle estimated yield of a predetermined number of processes out of the plurality of new processes, on the basis of an estimated yield of each of the predetermined number of processes. This increases accuracy of the middle estimated yield of the predetermined number of processes.
Accordingly, an object of the present invention is to provide the defect analysis method which makes it possible to quantitatively grasp the influence of the number of defects due to only a single process out of a plurality of processes on the yield of the device.